Quarter square analog multiplier



May 24, 1966 J. M. coLLlNGs ETAL 3,253,135

QUARTER SQUARE ANALOG MULTIPLIER Filed Feb. 20, 1962 Jerry M o//mga By V/f/or H. Sans/1m.

Mw/651A@ United States Patent O 3,253,135 QUARTER SQUARE ANALOG MULTIPLIER Jerry M. Collings, Concord, and Victor H. Sansum, Oakland, Calif., assignors to Systron-Donner Corporation, Concord, Calif., a corporation of California Filed Feb. 20, 1962, Ser. No. 174,438 6 Claims. (Cl. 23S-194) This invention relates -to analog multipliers and more particularly to quarter square analog multipliers.

In quarter square analog multipliers heretofore available, four squaring networks are required to obtain a quarter square multiplier. There is a need for a new and improved quarter square multiplier which requires fewer squaring networks and other components.

In general, it is an object of the presen-t invention to provide a quarter square analog multiplier which has fewer components `and which is less expensive.

Another object of the invention is to provide a multiplier of the above character in which only inputs of -i-x, -l-y are required to realize the product kxy at the output of the multiplier.l

Another o'bje-ct of the invention is to provide a multiplier of the above character which requires a maximum of three amplifiers.

Another object of the invention is to provide a quarter square analog multiplier of the above character which has improved characteristics.

Additional objects and fe-atures of the invention Will appear from the following description in which the preferred embodiment is set forth in detail in conjunction with the accompanying drawings.

Referring to the drawings:

The sole figure is a circuit diagram, partially in block form, of a quarter square analog multiplier incorporating our invention.

As shown in the figure, our quarter square analog multiplier has two input terminals T1 and T2 to which `are applied the signals x and y. Either of these signals may be of either polarity, that is, x may be a positive or a negative voltage, and y may be a positive or a negative voltage. For purposes of convenience, it has Ibeen assumed that both x and y are positive as indicated in the figure. However, in any event, both the opposites of x and y must be made available. Therefore, an inverter 11 is connected to the terminal T1 and supplies -x and inverter 12 is connected to the terminal T2 `and supplies -y. tional amplifier A2 with a feedback resistor R2-1. An input resistor R1-1 is connected to the operational amplifier A2. The feedback resistor is sized such that the output from the operational amplifier A2 has the same magnitude but is opposite in polarity to the input voltage. The inverter 12 is constructed in a similar manner and consists of an operational amplifier A3, feedback resistor R1-2 and an input resistor R2-2.

By examining the circuit diagram, it can be seen that terminals are provided which are identified as x, y, x, y, x, y, -x and y. The terminals marked x receive their voltage directly from the x input terminal T1 and the terminals marked y receive their voltage directly from the y input terminal T2. The terminals marked -x and y receive their voltages from the inverters 11 and 12 as hereinbefore described. These terminals are connected into resistive summing networks as shown.

`Each of the summing networks consists of a pair of matched resistors which are connected to a diode. Thus, diode CR-l conducts only when the sum of x-l-y is positive. As pointed out above, either x or y can be positive or negative. It is only when the positive voltage summed by the resistors R3-1 and R4-1 is positive that the diode The inverter 11 consists of an opera- 3,253,135 Patented May 24, 1966 CRI-1 conducts. If CR1-1 is conducting, CK2-1 will not be conducting because it is supplied with `the opposites of the voltages being supplied to the resistors R3-1 and R4-1 connected to the diode CRI-1. Similarly, either diode CRI-2 or CK2-2 may be conducting depending upon the voltages supplied. Both of these diodes only conduct when a negative voltage is presented to the diodes and only one will be conducting at a time.

The outputs from the diodes in the summing networks are connected to a pair of squaring networks consisting of a plurality of diodes and resistors as hereinafter described. The network which is `connected to the diodes CRI-1 and CR2-1 can be termed the x squaring network, whereas the network connected to the diodes CRI-2 and GRZ-2 can be termed the y squaring network. The outputs of the squaring networks are combined and supplied to an operational amplifier A1.

Means is provided on each of -the x and y squaring networks to provide a zero output when the input is zero. For this condition, there should be zero current flowing into the amplifier A1 for a zero voltage to appear at its output. The zero current flow at the input of amplifier A1 for zero signal outputis obtained by providing paths to ground for currents from the reference supplies. These paths to ground consist of diodes CR4-1 and CR3-1 for the x network and diodes CR4-2 and CR3-2 for the y network. Diodes CR4-1 through CR12-1 and CR4-2 through CR12-2 are back biased when the input signal lis zero and thus do not conduct current from the Ireference voltage supplies to amplifier A1. f

For the diodes in this multiplier, it has been found that it is preferable to utilize diodes of a silicon type. As is well known to those skilled in the art, such diodes have a voltage drop. This voltage drop created difiiculty in obtaining zero output for zero input because of the voltages across diodes CR4-1 and CR4-2. However, this voltage drop was cancelled .by providing diodes CR3-1 and CR3-2 in the x and y networks respectively. This diode in each lof the networks has across it a voltage having magnitude and which is opposite in polarity to the voltage drop in the associated diode CR4-1 or CR4-2 to provide a net voltage between associated resistors, resistors RS-l and R10-1 or R8-2 and R10-2, which is equal to zero. The currents producing voltage drops across diodes CR3-1 and CR3-2 are obtained from the plus and minus references to which the diodes are connected `through dropping resistors R7-1 and R7-2, respectively. Diodes CR3-1 and CR3-2 conduct at all times.

From the foregoing, it can be seen that the diodes CR3 and CR4 of each of the networks serve to clamp the input of the amplifier A1 to ground. This serves to eliminate the possibility of an output ysignal from the multiplier when input is zero. The resistors R7-1 and R7-2 ensure that exactly the proper amount of current will pass through the diodes CR3-1 and CR3-2, respectively, to obtain the proper voltage drop across the diodes and to thereby cancel the voltage drop which occurs across the diodes CR4-1 and CR4-2, respectively.

The -bias which is applied to the various diodes in each of the x and y networks is determined by the reference voltages and the resistors R29-1 and R29-2, respectively, and may be called the x gain adjust and y gain adjust, respectively. These controls permit adjustment of k, the scale factor of the output kxy; e.g. k=.01.

Now let it be assumed that there is a positive output from either the diode CRI-1 or GRZ-1 which represents k(x-{y). This positive voltage is supplied to the output amplifier A1 through the resistor R9-1. At a predetermined voltage as, for example, 10 volts, the diode CR4-1 stops conducting because the current from the x-i-y source exceeds that from the negative reference supplied through R29-1. As soon as CR4-1 stops conducting, there is less attenuation of the input signal because R8 is not grounded through the conducting diodes CRS and CR4. Current then flows through the resistor R9-1 to provide a change in the slope of the output of the amplifier A1. When the k(x-|y) voltage reaches another predetermined voltage such as volts, the diode CRS-1 begins conducting. Prior to this time, the diode CRS-1 was held cutoff because of the current coming from the negative reference supply. At 20 volts, the current arriving from the k(x-|y) signal source equals the current coming from the negative reference source to start the diode CRS-1 conducting. It should be pointed out that all the diodes CRS-1 through CRlZ-l are biased or held cuto by the negative reference until the k(x{-y) input voltage reaches the required level to overcome the bias. The current from the negative reference source fiows to ground because of the zero source impedance of the signal source and the zero source impedance at the amplifier junction T-3 for the amplifier A1. It is for this reason that these source impedances should be as near zero as possible.

As soon as CRS-1 begins conducting, there is another current path for the input signal to reach the junction of the amplifier A1 and, therefore, the transfer characteristic 4of the amplifier A1 takes on a steeper slope. This same procedure continues as the k(x|-y) voltage increases to provide additional current paths tothe junction T3 of the amplifier A1. Thus, as each diode starts conducting, the transfer characteristic of the amplifier takes on a still steeper slope. To obtain this steeper slope, it is necessary to increase the gain or transfer characteristic of the amplifier. However, the gain of the amplifier is not actually increased. It is merely the relationship between the input and the feedback resistance R31 which changes the transfer characteristic or the gain of the amplifier. However, in this embodiment, the feedback resistance R31 is constant. The diode network connected to the input of the amplifier A1, in effect, varies the input resistance to the amplifier to thereby increase the gain of the amplifier as the k(x{y) signal is increased.

As is well known to those skilled in the art, it is desirable that the output of the amplifier A1 approach the square law which is actually one-half of the parabola. The parabolic curve is approximated by dividing it into a predetermined number of straight line segments as, for example, ten segments, which are approximated in each of the squaring networks.

In the circuit diagram, certain of the components have been indicated as being omitted. Thus, resistors 14-1, 16-1, 18-1, 20-1 and 22-1 and resistors R15-1, 17-1, 19-1, 21-1, 23-1 and diodes CR7-1 through CRll-l have been omitted. Corresponding resistors and diodes for the y network have also been omitted. These squaring networks provide ten straight line segments which approximate the square law.

It was found that it was desirable that the reference source impedance for our multiplier be zero or close to it. However, it has been found that if the source impedance is not quite zero, the accuracy of our multiplier is not adversely effected because of the use of the voltage divider consisting of the resistor R29-1 and the other resistors in the network which effectively shunt the resistive impedance of the reference voltage supply. The resistor R29-1 for the x network and resistor R297-2 for the y network are normally the only resistors which are adjustable and are utilized to determine the scale factor of the multiplier.

The y squaring network operates in the manner similar to the x squaring network and for that reason, it will not be described in detail.

By way of example, one embodiment of our quarter square analog multiplier had the following components.

All Diodes 1N463 Resistors: K Ohms R3-1 50 R3-2 50 R3-3 50 R3-4 50 R3-5 50 R3-6 50 R3-7 50 R3-8 50 R7-1 100 R7-2 100 R8-1 8.04 RS-Z 8.04 R9-1 766 R9-2 766 R10-1 32.9 R10-2 32.9 R11-1 825 R11-2 825 R12-1 23.6 R122 23.6

RZZ-Z 5.83

From the foregoing, it can be seen that we have provided a new and improved quar-ter square analog multiplier in which the sums of x-i-y and x-y are obtained within the multiplier itself by the use of precision resistors so that they can be multiplied by means of square law networks provided in the multiplier. Thus, it can be seen that the x network produces a function which is a square of the sum of the two input voltages, Whereas the y network produces a negative of the square of the difference of the two input voltages. Both the x and y networks do the same thing. A sign reversal is obtained by inverting the diodes in one network as is readily apparent from the circuit diagram.

It is apparent from the foregoing that we have provided a new and improved quarter square analog multiplier in which and y are the only inputs Yrequired and in nwhich only three amplifiers are required for multiplication. In addition, only two squaring networks are required. Thus, the multiplier is simplified while still obtaining relatively great accuracy.

We claim:

1. In a quarter square analog multiplier, lirst and second terminals for receiving an input voltage on each terminal, lirst and second inverting means connected to each terminal for inverting the polarity of the voltage applied to the terminal, rst and second passive summing means connected to each of the terminals and to the output of the inverting means connected to each terminal for producing the sum and the dilerence of the two signals, first and second symmetrical biased diode squaring networks connected to said first and second surnming means for squaring the sum of the two signals and for `squaring the difference of the two signals, and means and means combining the outputs of the squaring networks,

2. A multiplier as in claim 1 wherein the two input signals and their inversions are available within the circuitry.

3. In a quarter square analog multiplier, a pair of input terminals having input voltages identitied as x and y applied -to the input terminals, inverting means including an operational amplifier connected to each of the terminals for supplying a voltage of equal magnitude but opposite polarity of the voltage connected to the input terminal, passive summing means connected to the input terminals and to the output of the inverting means connected to each terminal to provide k(x+y) and k(x-y), a pair of squan'ng networks connected to the outputs summing networks and producing k(x|y)2 and -k(xy)2, and means combining the outputs of the squaring networks to provide kxy.

4. A multiplier as in claim 3 wherein said summing means consists solely of pairs of resistors connected in parallel and a diode connected to each pair of resistors.

5. A multiplier as in claim 3 wherein each ot' the squaring networks consists of a plurality of diodes connected in parallel, means including a first reference source for maintaining the diodes cut off below predetermined voltages so that each diode conducts at a diierent predetermined Voltage, an additional diode connected to the parallel connected diodes, and means including a second reference source for biasing the additional diode in a direction opposite to the direction in which the other diodes are biased.

6. A multiplier as in claim 5 together with diode means connected to the additional diode for cancelling out the voltage drop occurring in the additional diode so that the output of the multiplier is zero when the input is Zero.

References Cited by the Examiner UNITED STATES PATENTS 2,697,201 12/1954 Harder 23S-197 X 2,900,137 8/1959 Giser 235--194 2,906,459 9/1959 I .Ovell 23S-194 2,995,304 8/1961 Reque 23S-194 3,031,143 4/1952 McCoy et :Ll 235-194 3,106,639 10/1963 Nathan 235-197 OTHER REFERENCES Electronic Analog Computers (Korn et al.), published by McG-raw-Hill Book Co., First Edition, page 214, 1952.

MALCOLM A. MORRISON, Primary Examiner.

H. E. WURST, I. KESCHNER, Assistant Examiners. 

1. IN A QUARTER SQUARE ANALOG MULTIPLIER, FIRST AND SECOND TERMINALS FOR RECEIVING AN INPUT VOLTAGE ON EACH TERMINAL, FIRST AND SECOND INVERTING MEANS CONNECTED TO EACH TERMINAL FOR INVERTING THE POLARITY OF THE VOLTAGE APPLIED TO THE TERMINAL, FIRST AND SECOND PASSIVE SUMMING MEANS CONNECTED TO EACH OF THE TERMINALS AND TO THE OUPUT OF THE INVERTING MEANS CONNECTED TO EACH TERMINAL FOR PRODUCING THE SUM AND THE DIFFERENCE OF THE TWO SIGNALS, FIRST AND SECOND SYMMETRICAL BIASED DIODE SQUARING NETWORKS CONNECTED TO SAID FIRST AND SECOND SUMMING MEANS FOR SQUARING THE SUM OF THE TWO SIGNALS AND FOR SQUARING THE DIFFERENCE OF THE TWO SIGNALS, AND MEANS AND MEANS COMBINING THE OUTPUTS OF THE SQUARING NETWORKS. 